| Model-checking continuous-time Markov chains A Aziz, K Sanwal, V Singhal, R Brayton ACM Transactions on Computational Logic (TOCL) 1 (1), 162-170, 2000 | 976* | 2000 |
| BDS: A BDD-based logic optimization system C Yang, M Ciesielski, V Singhal Proceedings of the 37th Annual Design Automation Conference, 92-97, 2000 | 345 | 2000 |
| It usually works: The temporal logic of stochastic systems A Aziz, V Singhal, F Balarin, RK Brayton, AL Sangiovanni-Vincentelli Computer Aided Verification: 7th International Conference, CAV'95 Liège …, 1995 | 314 | 1995 |
| Tight integration of combinational verification methods JR Burch, V Singhal Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 129 | 1998 |
| BDD based procedures for a theory of equality with uninterpreted functions A Goel, K Sajid, H Zhou, A Aziz, V Singhal Computer Aided Verification: 10th International Conference, CAV'98 Vancouver …, 1998 | 124 | 1998 |
| HSIS: A BDD-based environment for formal verification A Aziz, F Balarin, ST Cheng, R Hojati, T Kam, SC Krishnan, RK Ranjan, ... Proceedings of the 31st annual Design Automation Conference, 454-459, 1994 | 107 | 1994 |
| Minimizing interacting finite state machines: A compositional approach to language containment A Aziz, V Singhal, R Brayton, GM Swamy Proceedings 1994 IEEE International Conference on Computer Design: VLSI in …, 1994 | 59 | 1994 |
| Formula-dependent equivalence for compositional CTL model checking A Aziz, TR Shiple, V Singhal, AL Sangiovanni-Vincentelli Computer Aided Verification: 6th International Conference, CAV'94 Stanford …, 1994 | 57 | 1994 |
| BDD decomposition for efficient logic synthesis C Yang, V Singhal, M Ciesielski Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 53 | 1999 |
| Analysis of locking behavior in three real database systems V Singhal, AJ Smith The VLDB Journal 6, 40-52, 1997 | 51 | 1997 |
| The validity of retiming sequential circuits V Singhal, C Pixley, RL Rudell, RK Brayton Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 316-321, 1995 | 50 | 1995 |
| The case for retiming with explicit reset circuitry V Singhal, S Malik, RK Brayton Proceedings of International Conference on Computer Aided Design, 618-625, 1996 | 49 | 1996 |
| Robust latch mapping for combinational equivalence checking JR Burch, V Singhal Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998 | 47 | 1998 |
| Method for verifying properties of a circuit model V Singhal, JE Higgins US Patent 7,020,856, 2006 | 46 | 2006 |
| System and method for identifying design efficiency and effectiveness parameters for verifying properties of a circuit model CWN Ip, L Loh, V Singhal, H Wong-Toi, S Myint US Patent 7,159,198, 2007 | 44 | 2007 |
| A dual granularity and globally interconnected architecture for a programmable logic device R Cliff, B Ahanin, LT Cope, F Heile, R Ho, J Huang, C Lytle, ... Proceedings of IEEE Custom Integrated Circuits Conference-CICC'93, 7.3. 1-7.3. 5, 1993 | 40 | 1993 |
| Equivalences for fair kripke structures A Aziz, V Singhal, F Balarin, RK Brayton, AL Sangiovanni-Vincentelli Automata, Languages and Programming: 21st International Colloquium, ICALP 94 …, 1994 | 39 | 1994 |
| Method and system for combinational verification having tight integration of verification techniques JR Burch, V Singhal US Patent 6,308,299, 2001 | 37 | 2001 |
| Trace based method for design navigation V Singhal, JE Higgins, AN Singh US Patent 7,137,078, 2006 | 35 | 2006 |
| Guidelines for creating a formal verification testplan H Foster, L Loh, B Rabii, V Singhal Proc. DVCon, 2006 | 35 | 2006 |
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